Not Applicable.
Not Applicable.
Not Applicable.
(1) Field of the Invention
The invention relates to a field effect transistor structure and a method of its manufacture, and in particular to an field insulated gate field effect transistor structure having a drift region and a field plate over the drift region and method of manufacture.
(2) Description of Related Art
In an insulated gate field effect transistor (IGFET) structure, a semiconductor channel region between source and drain is controlled by a gate insulated from the channel. IGFET structures are generally implemented as Metal Oxide Semiconductor (MOS) structures.
A double diffused MOS (DMOS) structure may be used in which a long lateral path, known as the drift region, extends between drain and source diffusions. The drift region attenuates any high voltages applied between drain and source down to around 20 V in the channel region controlled by the gate.
In order to maximise the voltage capability of the transistor, the drift region would ideally be long and or lightly doped. Unfortunately, these properties would mean that the drift region would contribute a relatively high resistance to the overall device when the transistor is on. To address this, it is known to dope the drift region with an appropriate doping profile and to choose its thickness such that the reversed bias junctions between the MOSFET channel and source and between the channel and the substrate deplete the entire drift region of charge carriers when the device is turned off. This creates a uniform electric field in the drift region when a large voltage is applied across the transistor when switched off, which maximises the breakdown voltage since there are no peaks in the electric field to initiate premature avalanche breakdown. The fully depleted drift region is said to be in a RESURF (reduced surface field) condition. In a RESURF structure, the full thickness of the drift region is depleted when the device is turned off.
A lateral MOS device using this technique is described in U.S. Pat. No. 5,412,241 to Merchant, assigned to Philips Electronics North America Corp. The device is illustrated in FIG. 1.
The device is a silicon on insulator (SOI) device having a layer of silicon 101 formed on a buried oxide layer 103 on a semiconductor substrate 105. Source 107 and drain 109 regions are formed in the silicon, and connected to source 108 and drain 110 contacts respectively.
A gate layer 111 is provided over part of the silicon layer 101 which forms a channel, separated from the channel by a gate oxide 112. The gate layer is connected to a gate contact 113. The gate controls conduction between source 107 and drain 109, as is well known.
Between the channel and the drain a drift region 119 is provided in the silicon layer 101 to allow large voltages (e.g. 100 V or more) to be applied between source and drain. A large voltage applied across source and drain may be at least partially dropped in the drift region thus reducing the voltage dropped in the channel.
A field plate 115 is formed integrally with the gate layer 111 over the LOCOS oxide layer 114 and extends laterally over the drift region 119 in the silicon layer 101. When the device is turned off, the field plate depletes the drift region to provide a RESURF effect.
The drift region 119 is protected from the effects of an impinging electric field, such as may be caused by moisture or other charged contaminants on the surface of the wafer, by the field plate 115. Electric fields will terminate on the field plate 115. Further, because the field plate is connected to the gate the drift region 119 may be depleted both from the top and the bottom which means that the device can be designed with a higher doping level in the drift region than would otherwise be possible since the drift region can more readily be depleted. This means that the device of U.S. Pat. No. 5,412,241 can be made with a low on-resistance.
Such silicon on Insulator device structures such as these exhibit, by virtue of their structure, low values of the capacitance between gate and drain (Cgd) and the charge needed to be supplied through gate and drain to switch the device (Qgd). These low values of Cgd and Qgd result in a rapid response to changes in gate voltage. However, it would still be beneficial to still further improve switching speed.
The above example relates to a Silicon on Insulator device. However similar considerations apply to other forms of IGFET devices. The need to improve switching speed remains. In particular there is a need for devices that combine improved switching speed with the capability to cope with high voltages between source and drain, preferably in combination with low on-resistances.
According to the invention there is provided an insulated gate field effect transistor structure, comprising: a source region and a drain region laterally spaced in a semiconductor layer; a drift region adjacent to the drain region in the semiconductor layer between the source region and the drain region; a channel arranged in the semiconductor layer between the source region and the drift region; an insulated gate electrode arranged over the channel; a field plate arranged over the drift region separated from the drift region by a capacitance oxide layer; and an electrical interconnection between the source region and the field plate to electrically connect the source region and the field plate.
The source-connected field plate acts as a Faraday screen between gate and drain so reducing Cgd and hence the charge needed to be applied through gate and drain to decrease the switching time.
In contrast, the prior art gate-connected field plate has a different function, of protecting the drift region and allowing the drift region to be depleted by a suitable voltage on the gate and hence on the field plate. This prior art arrangement will normally increase Cgd and hence increase switching time. In contrast, the source-connected field plate decreases switching time.
At first sight, it might appear that the increase in gate-source capacitance Cgs would counteract any benefit of the reduced Cgd. However, this is not the case. In conventional circuit arrangements, the Miller effect comes into play. The total input capacitance Cinput is given by the sum of Cgs and the Miller capacitance, CM=(1+gMRL)Cgd, where RL is the load resistance and gM the transconductance. This means that the switching speed may be dominated by the contribution from Cgd so that the device according to the invention has an improved switching speed.
The transistor structure is preferably formed to have a source and drain of a first conductivity type. The drift region may be of the same conductivity type but of lower doping, and the channel may be formed in a body region of opposite conductivity type. The first conductivity type may be n-type.
The field plate may be fabricated from any convenient conducting material, such as polysilicon, polycide or silicide. The field plate may be doped n+ or p+. The field plate may conveniently made from the same layer as the gate electrode.
The drift region may be linearly graded, i.e. it may have a concentration of dopant that varies linearly, decreasing away from the drain. This may result in an improved breakdown performance compared with a drift region of constant concentration.
Preferably, the doping concentrations are such that the depletion region spreads throughout the drift region when the transistor is turned off, that is to say the transistor is a reduced surface field (RESURF) transistor. The depletion region may extend into the body and drain.
In embodiments, a device according to the invention may be formed from a substrate having source and drain diffusions and a graded drift region of a first conductivity type embedded in it. In such devices, a backside contact may be formed on the substrate to allow the substrate may be biased to the source voltage to optimise the performance.
Alternatively, embodiments of the invention may be implemented in a SOI structure, with a substrate, a buried oxide layer on the substrate and a silicon layer deposited on the buried oxide layer. Source, drain, channel and drift regions may be formed from implantations in the deposited silicon layer. Such SOI structures offer advantages such as intrinsically lower capacitance.
The invention also relates to a method of manufacturing a transistor structure including, in any order, the steps of: forming a drift region and a channel region in a semiconductor body layer; forming an oxide layer over the semiconductor body layer; forming an upper conductive layer over the oxide layer, the upper conductive layer defining a gate electrode and a field plate; diffusing source and drain diffusions to form source and drain in the semiconductor body layer; and depositing a metallisation layer defining a source contact connected to the source region and to the field plate region, a gate contact connected to the gate region and a drain contact connected to the drain region.